Multirate hybrid CT/DT cascade ΣΔ modulators with decreasing OSR of back-end DT stages

This paper presents novel architectures of multirate hybrid cascade continuous-time/discrete-time !" modulators that take advantage of the potentially faster operation of the continuoustime part of the circuit, while keep a reduced sampling operation of the back-end discrete-time stages. Compared to conventional multirate !" modulators, the proposed architectures use a higher sampling rate in the front-end (continuous-time) stage of the modulator, whereas the back-end (discrete-time) stages operate at a lower rate. It is demonstrated that the intrinsic aliasing signal can be cancelled in the digital domain, with no additional analog hardware required. The resulting !" topologies are potentially faster than conventional multirate !" modulators, more power efficient than hybrid monorate architectures and more robust than cascade continuous-time implementations. The combination of these features results in a new class of !" modulators, very suited for the implementation of analog-to-digital converters in the next generation of broadband wireless telecom systems.